Description
RTL hardware designs can be synthesized and transformed in an open-source command workflow. It is used by FPGA and digital-design developers to process Verilog and related design files into implementation-ready forms.
FICHA · AUR
yosys-git
A framework for RTL synthesis
- Build tool
- CLI
- Dev
- Launchable
- Runs in terminal
official+codex · reviewed · Jun 5, 2026 description in
en How to run
yosys
Commands: yosys
Permissions
Permissions not analysed for this source yet.