FICHA · AUR

python-litepcie

Small footprint and configurable PCIe core

  • PCIe endpoint and host logic FPGA core
  • LIBRARY
  • HARDWARE
  • Dependency only
official+codex · reviewed · Jun 3, 2026 description in en

Description

PCIe endpoint and host logic can be integrated into FPGA and SoC designs through the LiteX ecosystem. Hardware developers use this core for PCI Express device designs, simulation, synthesis, and board bring-up. Generated gateware can affect real devices, so timing, pinout, and test coverage need review.

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