Description
Nightly RTL synthesis tooling lets hardware developers test recent Yosys changes before a stable release. It processes digital design files for FPGA and ASIC workflows, with the instability expected from nightly builds.
FICHA · AUR
Yosys Open SYnthesis Suite, A framework for RTL synthesis
en Nightly RTL synthesis tooling lets hardware developers test recent Yosys changes before a stable release. It processes digital design files for FPGA and ASIC workflows, with the instability expected from nightly builds.
yosys
Commands: yosys
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